is a research scientist in Intel’s Parallel Computing Lab, part of the Microprocessor and Programming Research division of Intel Labs. His research interests generally relate to parallel applications and architectures. His recent work includes mapping emerging applications on parallel computer architectures, tools and languages to aid parallel workload development, and next-generation computer architectures. Read More
Faye Briggs Intel Fellow, Datacenter and Connected Systems Group and Chief Server Architect
Fayé Briggs is an Intel Fellow and chief server architect for the Datacenter and Connected Systems Group at Intel Corporation. He is responsible for ensuring that Intel’s multi-core and many-core-based server platform architectures for the data center, achieve best-in-class attributes, such as performance, reliability, availability, serviceability, power-efficiency, and security in each server market segment. Briggs has had a leadership role in developing multiple generations of innovative multiprocessor server platforms and chipset designs, including all current front side bus-based Intel® Xeon® dual- and multi-processor server chipsets and platform architectures. He conceptualized the first Intel point-to-point coherent scalability port for 2P-16P scalable architecture family of 870 server chipsets for Itanium® processor-based and Intel Xeon processor-based servers and led development of the devices. Briggs served as the Intel Fellow-In-Residence for China during 2011-2012. Briggs has published numerous technical papers on processor and multiprocessor architectures and micro-architectures, memory ordering, cache coherence and system performance. He is the co-author of the McGraw-Hill-published textbook Computer Architecture and Parallel Processing. Briggs has been awarded four patents and received an Intel Achievement Award for the successful definition and execution of Intel’s first quad core products. Briggs received his bachelor’s degree in engineering from Ahmadu Bello University, Nigeria. He received his master’s degree in electrical engineering from Stanford University, and his doctorate in electrical and computer engineering from the University of Illinois, Urbana-Champaign.
Michael Carey Bren Professor of Information and Computer Sciences at the University of California, Irvine
Prior to rejoining academia in 2008, Dr. Carey was a Senior Engineering Director at BEA Systems, Inc., where he landed after the Internet startup bubble burst in 2001. At BEA he was chief architect for the BEA AquaLogic Data Services Platform. Prior to joining BEA, Dr. Carey spent a dozen years on the University of Wisconsin-Madison computer science faculty, five years as an IBM Almaden database researcher and research manager, and a year and a half at an e-commerce software startup called Propel Software. In addition to UW-Madison and UC Irvine, he has taught graduate computer science classes at U.C. Berkeley and Stanford. Dr. Carey is an ACM Fellow, a member of the National Academy of Engineering, and a past recipient of the ACM SIGMOD Edgar F. Codd Innovations Award and ACM SIGMOD Contributions Award. He has co-authored numerous conference and journal articles on topics related to database management systems and middleware. Dr. Carey is currently leading the ASTERIX BDMS (Big Data Management System) project at UC Irvine.
Pradeep Dubey Intel Fellow and Director, Parallel Computing Lab
Pradeep is both a member of the research team and the advisory board. He is the Intel Principal Investigator (PI) for the Big Data ISTC and is an Intel Fellow and director of the Parallel Computing Lab, a part of the Intel Labs organization at Intel Corporation. Since 2003, he has led a team of top researchers focused on state-of-the-art research in highly parallel computing. Dubey and his team are charged with defining computer architectures that can efficiently handle new compute- and data-intensive application paradigms for future computing environments, and deriving product differentiation opportunities for Intel multi-core and many-core platforms. Read More
Pat Hanrahan CANON Professor of Computer Science and Electrical Engineering at Stanford University
Dr. Hanrahan teaches computer graphics at Stanford. His current research involves visualization, image synthesis, virtual worlds, and graphics systems and architectures. Before joining Stanford he was a faculty member at Princeton.Pat has also worked at Pixar where he developed developed volume rendering software and was the chief architect of the RenderMan(TM) Interface – a protocol that allows modeling programs to describe scenes to high quality rendering programs. In addition to PIXAR, he has founded two companies, Tableau and PeakStream, and served on the technical advisory boards of NVIDIA, Exluna, Neoptica, VSee and Procedural.Professor Hanrahan has received three university teaching awards. He has received two Academy Awards for Science and Technology, the Spirit of America Creativity Award, the SIGGRAPH Computer Graphics Achievement Award, the SIGGRAPH Stephen A. Coons Award, and the IEEE Visualization Career Award. He was recently elected to the National Academy of Engineering and the American Academy of Arts and Sciences.
James P. Held Intel Fellow, Intel Labs Director, Microprocessor and Programming Research
As director of Microprocessor and Programming Resear ch, Jim Held leads a team conducting research in microarchitecture, parallel computing and programming systems to develop key technologies for future microprocessors and platforms. Since joining Intel in 1990, Held has served in a variety of positions working on computer supported collaboration technology and Intel Native Signal Processing (NSP) infrastructure. He served as staff principal architect in the Media and Interconnect Technology Lab in IAL and as the Lab Director in CTG, managing the Volume Platforms Lab. As a Senior Principal Engineer in the Microprocessor Technology Lab, he conducted research on extensible processor architecture, multi-core processor architecture and helped develop Intel’s virtualization technology strategy. From 2005-2011 he led a virtual team of senior architects conducting Intel Lab’s Tera-Scale Computing Research. Before coming to Intel, Held worked in research and teaching capacities in the Medical School and Department of Computer Science at the University of Minnesota. He is a Member of the IEEE Computer Society and the Association for Computer Machinery (ACM). Held earned a B.S. in Chemical Engineering in 1972 and an M.S. (1984) and Ph.D. (1988) in Computer and Information Science, all from the University of Minnesota.
Randy Katz Professor, University of California, Berkeley
Randy Katz received his undergraduate degree from Cornell University, and his M.S. and Ph.D. degrees from the University of California, Berkeley. He joined the Berkeley faculty in 1983, where since 1996 he has been the United Microelectronics Corporation Distinguished Professor in Electrical Engineering and Computer Science. He is a Fellow of the ACM and the IEEE, and a member of the National Academy of Engineering and the American Academy of Arts and Sciences. In 2007, he received an honorary doctorate from the University of Helsinki. He has published over 250 refereed technical papers, book chapters, and books. His textbook, Contemporary Logic Design, has sold over 100,000 copies in two editions, and has been used at over 200 colleges and universities. He has supervised 49 M.S. theses and 39 Ph.D. dissertations (including one ACM Dissertation Award winner and ten women). His recognitions include thirteeen best paper awards (including one “test of time” paper award and one selected for a 50 year retrospective on IEEE Communications publications), three best presentation awards, the Outstanding Alumni Award of the Computer Science Division, the CRA Outstanding Service Award, the Berkeley Distinguished Teaching Award, the CS Division’s Diane S. McEntyre Award for Excellence in Teaching, the Air Force Exceptional Civilian Service Decoration, the IEEE Reynolds Johnson Information Storage Award, the ASEE Frederic E. Terman Award, the IEEE James H. Mulligan Jr. Education Medal, the ACM Karl V. Karlstrom Outstanding Educator Award, and the ACM Sigmobile Outstanding Contributor Award. In the late 1980s, with colleagues at Berkeley, he developed Redundant Arrays of Inexpensive Disks (RAID), a $15 billion per year industry sector. While on leave for government service in 1993-1994, he established whitehouse.gov and connected the White House to the Internet. His BARWAN Project of the mid-1990s introduced vertical handoffs and efficient transport protocols for mobile wireless networks. His current research interests are the architecture of Internet Datacenters, particularly frameworks for datacenter-scale instrumentation and resource management. With David Culler and Seth Sanders, he has started a new research project on Smart Energy Networks, called LoCal. Prior research interests have included: database management, VLSI CAD, high performance multiprocessor (Snoop cache coherency protocols) and storage (RAID) architectures, transport (Snoop TCP) and mobility protocols spanning heterogeneous wireless networks, and converged data and telephony network and service architectures.
Geoff Lowney Intel Fellow Chief Technology Officer, Developer Products Division of the Software and Solutions Group
Geoff Lowney is responsible for using advanced compiler technology to improve the performance and usability of Intel Architecture processor family products.He joined Intel as part of a June 2001 agreement with Compaq Computer Corporation that called for the transfer of microprocessor engineering and design expertise to Intel.Prior to joining Intel, he was a Compaq Fellow and Director of Compiler and Architecture Development for the Alpha Microprocessor Group. His responsibilities included developing compiler technology and tuning compilers for Alpha systems, providing architectural direction to the microprocessor design teams and designing Alpha architecture extensions.Before joining Digital Equipment Corporation in 1991, Lowney was a Consulting Engineer at Hewlett-Packard from 1990 to 1991. From 1984 to 1990, he was Director of Compiler Development at Multiflow Computer. Lowney received his doctorate and master’s degrees in computer science and his bachelor’s degree in mathematics from Yale University in 1983, 1978 and 1975, respectively. He holds 11 patents in computer architecture and compiler technology.
Ofri Wechsler Intel Fellow, Platform Engineering Group Director, Visual and Parallel Architecture Group
Ofri Wechsler is an Intel Fellow and director of Visual and Parallel Architecture Group (VPG) for the Platform Engineering Group at Intel Corporation. In this role Wechsler is responsible for the architecture development of the Many Integrated Cores (MIC) product line including Knights Corner, Knights Landing and Knights Hill. In addition Wechsler is also responsible for the Processor GFX (PG) media architecture from the Skylake generation and beyond. In the last two years Wechsler also led the “IA GFX Proof-of-concept” attempting to to implement a software rendering 3D pipeline on a MIC architecture.Prior to heading VPG Architecture Wechsler spent 10 years leading the CPU architecture team in in Israel. In this role Wechsler was responsible for the architecture development of many CPU generations including Skylake, Sandy Bridge, Ivy Bridge, Merom, Penryn, Banias, Dothan and Yonah. Previously, Wechsler served as platform architect for the Timna platform. He also served as manager for the Israel Design Center Architecture Validation team, responsible for the validation of the P55C version of the Intel® Pentium® processor. Wechsler joined Intel in 1988 as a design engineer for the i860.Wechsler received his bachelor’s degree in electrical engineering from Ben Gurion University, Beer Sheva, Israel, in 1989. He has four U.S. patents